The present invention relates to amplifiers and, more particularly, to a tuned switching power amplifier.
Amplifiers are commonly used to increase the strength of electrical signals. To increase the strength of an electrical signal, typically, the electrical signal is used to control a flow of energy from a DC power source, e.g., a battery, to produce an output signal that varies in the same way as the electrical signal but has a larger amplitude. Generally, it is desirable to efficiently amplify the electrical signal using a minimal amount of power to reduce energy costs and increase battery life, for example.
One method for efficiently amplifying electrical signals is disclosed in U.S. Pat. No. 3,919,656 to Sokal et al., entitled High-Efficiency Tuned Switching Power Amplifier, incorporated fully herein by reference. Additionally, U.S. Pat. No. 3,919,656 contains a detailed discussion of power amplifiers.
FIG. 1 is a circuit diagram of a tuned switching power amplifier 100 as disclosed in U.S. Pat. No. 3,919,656. The amplifier 100 includes a switch 102 responsive to an input signal from a signal source 104, a DC power source 106, and a load network 108 to create a transient response across the switch 102 and pass an amplified version of the input signal to a load 110. In operation, the switch 102 controls the flow of current from the DC power source 106 based on the input signal to generate an output signal at the load 110 having a greater amplitude than the input signal at the same frequency. The operating frequency of the amplifier 100 is its fundamental frequency.
In the amplifier 100, power may be wasted by the switch 102 in the form of heat when current is flowing through the switch 102 at the same time there is a voltage drop across the switch 102. Accordingly, to increase efficiency, the amplifier 100 is designed to: a) minimize the voltage across the switch 102 when appreciable current flows through it; b) minimize the current flowing through the switch 102 when appreciable voltage exists across it; and c) minimize the duration of simultaneous appreciable voltage across the switch 102 and current through the switch 102.
The load network 108 functions to produce a transient response across the switch 102 that satisfies the above design conditions. The load network 108 includes a current feed choke 112, a bypass capacitor 114, a parallel capacitor 116, a frequency filter 118, and a series inductor 120. The current feed choke 112 may be a quarter-wave transmission line (TL), i.e., a TL having an electrical length of 90xc2x0 in reference to the fundamental frequency, with negligibly small inductive susceptance for supplying essentially a constant current during the operation of the amplifier 100. If the inductive susceptance of the current feed choke 112 is not negligibly small, the capacitance of the parallel capacitor 116 is increased, thereby increasing the susceptance of a path containing the parallel capacitor 116 and effectively removing the current feed choke 112 from the amplifier 100 at the fundamental frequency. The frequency filter 118 includes a capacitor 122 and an inductor 124, and is designed so that only signals at the fundamental frequency are allowed to pass through the frequency filter 118, i.e., the frequency filter 118 is tuned to the fundamental frequency.
FIG. 2 illustrates the impedance as seen by the switch 102 at the fundamental frequency. At the fundamental frequency, the current feed choke 112 acts as an infinite impedance and the frequency filter 118 acts as a short. Therefore, the resultant impedance seen by the switch 102 can be represented by the parallel capacitor 116, the series inductor 120, and the impedance of the load 110. Accordingly, the parallel capacitor 116 and the series inductor 120 are the primary elements for producing a desired transient response across the switch 102.
Often, the size of an amplifier 100 is an important criteria depending on the application for which the amplifier 100 will be used. If an amplifier 100 having a small form factor is desired, a current feed choke 112 implemented using a TL with an electrical length of 90xc2x0 may inhibit a reduction in the size of the amplifier. In addition, the series inductor 120 may adversely contribute to the size of the amplifier 100 and in conjunction with the parallel capacitor 116 may produce an undesirable impedance transformation at the output of the amplifier 100. Accordingly, there is a need for an efficient tuned switching power amplifier having less series inductance and a parallel TL with an electrical length of less than 90xc2x0. The present invention fulfills this need among others.
The present invention provides for a switching tuned power amplifier apparatus and method that overcomes the aforementioned problems by placing a parallel capacitor and a parallel TL having an electrical length of less than 90xc2x0 across a switch within the amplifier. The parallel capacitor and parallel TL create a transient response across the switch that minimizes current and voltage existing across the switch simultaneously. By using a capacitor and a TL having an electrical length of less than 90xc2x0 in parallel across the switch, efficient tuned switching power amplifiers having smaller form factors and desirable impedance transformation can be realized.
One aspect of the present invention is a switching amplifier apparatus for amplifying an input signal having a fundamental frequency to develop an output signal with the same frequency at a load. The amplifier includes a switch having a control for receiving the input signal, the switch responsive to the input signal to turn the switch on and off, the switch further having first and second terminals, the first and second terminals having a low impedance therebetween when the switch is on and having a high impedance therebetween when the switch is off, a load network coupled to the switch to deliver the output signal to the load, the load network including a TL of a determined length coupled between the first and second terminals to develop a parallel inductance across the switch and a parallel capacitor coupled between the first and second terminals to develop a parallel capacitance across the switch, a DC power source for supplying DC power to the TL, the parallel capacitor, and the switch. The TL and the parallel capacitor create a transient response across the switch that insures that, as the switch transitions from on to off, the voltage across the first and second terminals remains low until the current through the first and second terminals is substantially zero, and, prior to the switch""s transition from off to on, the voltage across the first and second terminals and the voltage time derivative are substantially zero.
Another aspect of the invention is a method for amplifying an input signal having a fundamental frequency to develop an output signal with the same frequency at a load. The method includes applying the input signal to a switch responsive thereto, developing parallel inductance across the switch with a TL of a determined length, developing parallel capacitance across the switch, supplying DC voltage to the switch, the parallel inductance, and the parallel capacitance, wherein the parallel inductance and capacitance develop a transient response across the switch to insure the voltage across the switch remains low, as the switch transitions from on to off, until the current through the switch is substantially zero, and the voltage across the switch and the voltage time derivative are substantially zero prior to the switch""s transition from off to on.